Homework 6

Due Sept. 26

  1. What is the quiescent state of the S and R inputs to an SR latch built of two NAND gates?
  2. The 4 3 memory of Fig. 3-28 uses 22 AND gates and three OR gates. If the circuit were to be expanded to 256 8, how many of each would be needed?
    Screen_Shot_2014-09-17_at_3.55.38_PM.png
  3. A computer with a 32-bit wide data bus uses 1M 1 dynamic RAM memory chips. What is the smallest memory (in bytes) that this computer can have?
  4. Assume that the block transfer of Fig. 3-42 were done on the bus of Fig. 3-38. How much more bandwidth is obtained by using a block transfer over individual transfers for long blocks? Now assume that the bus is 32 bits wide instead of 8 bits wide. Answer the question again.

    Screen_Shot_2014-09-17_at_3.57.58_PM.pngScreen_Shot_2014-09-17_at_3.59.33_PM.png
  5. Why have multicore chips suddenly appeared? Are there technological factors that have paved the way? Does Moore’s law play a role here?
  6. Modern CPU chips have one, two, or even three levels of cache on chip. Why are multiple levels of cache needed?
  7. Suppose that a CPU has a level 1 cache and a level 2 cache, with access times of 1 nsec and 2 nsec, respectively. The main memory access time is 10 nsec. If 20% of the accesses are level 1 cache hits and 60% are level 2 cache hits, what is the average access time?
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Topic revision: r2 - 2014-09-18 - JimSkon
 
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