Homework 8

Ch 4.1

1. What are the four steps CPUs use to execute instructions?

2. In Fig. 4-6, the B bus register is encoded in a 4-bit field, but the C bus is represented as a bit map. Why?

3. In Fig. 4-6 there is a box labeled ‘‘High bit.’’ Give a circuit diagram for it.

4. When the JMPC field in a microinstruction is enabled, MBR is ORed with NEXT AD- DRESS to form the address of the next microinstruction. Are there any circumstances in which it makes sense to have NEXT ADDRESS be 0x1FF and use JMPC?

5. Suppose that in the example of Fig. 4-14(a) the statement k = 5; is added after the if statement. What would the new assembly code be? Assume that the compiler is an optimizing compiler.

6. Give two different IJVM translations for the following Java statement: i = k + n + 5;

7. Give the Java statement that produced the following IJVM code:

ILOAD j
ILOAD n
ISUB
BIPUSH 7
ISUB
DUP
IADD
ISTORE i

*

Topic revision: r1 - 2014-10-01 - JimSkon
 
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