Lab 6 - Simple Manual Computer

Step 1:

Consider the following modification from the previous lab with a memory added:

DemoSystem4.jpg

Microinstructions

bits meaning
0-7 Memory address or immediate operand
8 0 - Select immediate operand
1 - Select ALU
9-11 ALU Function:
000 A ^ B
001 A v B
010 B'
011 A+B+Cin
100 A
101 B
110 -A
111 B-A
12 Carry In
13-18 Reg Load:
13 - Mem
14 - A
15 - B
16 - C
17 - D
18 - H
19-21 Reg Sel:
Mem = 000
A = 001
B = 010
C = 011
D = 100

Consider:

  1. the "Operand" (bits 0-7) of the control word can now be used for either an "immediate" value, or as an address for memory. What is the significance of this?
  2. Bit 8 is used to select whether the input to the registers is from the ALU or the operand field in the microcode.
  3. Explain how the memory is written to, and read from in this example.

Step 2: Identify Microinstructions

Consider all the possible microinstructions. Finish the table below:

  • SR = source register A, B, C, D, H
  • RL = destination register list, e.g. A, C or C, D, Mem. A,C is 001010. C, D, Mem is 011001.
  • Mem[address] = value of Memory at address address.
  • OPADD - address/value in microinstruction
  • x - Don't care
Microinstruction Binary Example Binary
RL = H + SR SR RL 0 011 1 xxxxxxxx A,H = H + B 010 100010 0 011 1 00000000
Mem[add],RL = H + SR SR RL 0 011 1 Address Mem[4] = H + C 011 000001 0 011 1 00000100
RL = Const xxx RL 0 xxx 0 Const H = 6 000 100000 0 000 0 00000110
Mem[add] = Const Can't do, why?    
RL = Const   C, H = 18  
RL = Mem[Add]      
RL = SR + 1      
Mem[add] =-SR      
RL = H + SR + 1      
Mem[add] = H + SR      
Mem[add] = Mem[add] + SR + 1      

Step 3:

Build the system above using the circuit from your previous lab. Write and test a microprogram to do the following:

Memory Address Name Value
00000000 W 0
00000001 X 14
00000010 Y -4
00000011 Z 7

W = (X - Z) + Y

Z = W + Y

Step 4: (REDACTED)

Notice that this particular artitecture does not have an MDR, MAR and PC. The problem is that real memory cannot really be accessed directly, but through buffer registers due to speed differences between the CPU and memory.

Modify the design to:
  1. Add a MAR, MDR and PC
  2. Make all reads from to memory to occur by placing a value in the MAR, and reading from the MDR.
  3. Make all writes to memory occur by placing a value in the MAR, and asserting a "write" bit to write the current contents of the MDR.
  4. Create a circuit so that when the "fetch" bit is set, the contents of the PC (rather than the MAR) are used to retrieve the contents from memory into a special new register called the IR (instruction register), and the PC is also incremented.
Hints:
  • The register decoder is a 4x16, so there is room for selecting the additional registers.
  • You will no longer need the register decoder to directly select memory (since we now go through the MAR)
  • The MAR and PC can BOTH address into memory. You will need a way to select which address is placed on the address bus of the memory.
  • The "write" and "fetch" bits are NEW bits in the microcontrol memory. The "write" bit signals to move the contents of the MDR into MEM[MAR]. The "fetch" bit signals to move MEM[PC] into the new IR register.
  • You will also need a new bit to select memory operations, "memop". In order to read from memory you should set "write" to 0, and "memop" to 1. To write, set "write" to 1, and "memop" to 1
  • As mentioned in class, you will need circuitry to route the data input to the PC and MDR

Step 5

  1. (REDACTED)Make a new table defining the microinstruction format of the new machine micro-acrchitecture.
  2. (REDACTED) Devise and write up a test to check the operation of step 3. Explain how you are checking all cases, and show and comment the needed microinstructions to test the system out.
  3. Write up a lab report with answers to everything above, embedded pictures of the system, with full explainations.
  4. Describe the problems you had with this labs, what you learned, and how it could be better.
Topic attachments
I Attachment Action Size Date Who Comment
Jpgjpg ClockPhaseGenerator.jpg manage 19.8 K 2012-09-14 - 20:44 JimSkon Clock Generator
Jpgjpg DemoSystem4.jpg manage 73.2 K 2012-10-23 - 13:27 JimSkon Simple System with Memory
Jpgjpg SimpleComputer.jpg manage 69.5 K 2012-09-14 - 20:44 JimSkon Simple Computer
Circcirc SimpleComputer1.circ manage 18.6 K 2012-09-14 - 20:51 JimSkon Simple Computer
Circcirc SimpleComputerROM.circ manage 13.1 K 2012-09-14 - 20:51 JimSkon Simple Computer with ROM decoder logic
Jpgjpg SimpleComputerRom.jpg manage 50.4 K 2012-09-14 - 20:58 JimSkon Simpel Computer Using a ROM
Topic revision: r10 - 2012-12-10 - JimSkon
 
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