Computer Organization and Architecture

Exam 1 Practice

Fall 2014

  1. To transmit data bits 0110, the correct even parity seven bit Hamming Code is (bits ordered 7654321, place the 3 extra bits in location 765, e.g. PPP0110)

  2. Compare characteristic of RAM, ROM, PROM, EPROM, EEPROM memory. What are the best uses of each?

  3. A given memory chip has 22 address pins and 16 data pins. How many bits are in the memory? How many bytes? How many words? What is the smallest addressable unit?

  4. A given memory chip has 10 address pins and 4 data pins. Draw the chips with it's inputs. What is the size of the chip in bits/bytes? Draw a circuit using two chips to make a memory 8 bits wide. Next draw a circuit to make a memory 4-bits wide, but with twice as many 4-bit words as a single chip.

  5. What is DRAM and SRAM? What is the advantage of each?

  6. Convert 42 and -17 to eight bit 2-s complement values.

  7. How does the bus width of a CPU affect the performance and operations of a computer. What is the difference between the address bus and data bus? What is a control bus?

  8. Suppose that a bus has 32 data lines and requires 6 cycles of 200 nsecs each to transfer data. What I the bandwidth of this bus ?.

  9. What is meant by the word size of a computer? What does this have to do with the sizes of the data and address bus?

  10. What is a interrupt and what are they used for? How do they work?

  11. What is von Neumann architecture

  12. What I propagation delay and why is it important?

  13. How can a NAND gate be used to make other gates?

  14. What I meant by microcode, microprogramming? Why is this method used?

  15. What is the significance of RISC and CISC designs? Advantages of each? How does each work?

  16. Explain pipelining, superscalar processing, array processor, vector processor, caching. How does each work?

  17. A certain CPU has a two-level cache . The first-level cache has an access time of 4 nano sec, the second-level cache has an access time of 30 nano sec, and memory has an access time of 80 nano sec. If the hit ratio for the first-level cache is 80% and the hit ratio for the second-level cache is 15%, what is the mean access time for this memory system?

  18. Calculate the bus bandwidth required to display ful HD (1920x1080) true-color (24 bits per pixel) at 60 frames/sec. Assume that the data must pass over the bus twice, once from the hard disk to memory, and once from the memory to the video card.

  19. What is word alignment, and why is it significant?

  20. Design:

  • A 2x4 decoder

  • A 8x1 multiplexer

  • 4x4 memory circuit

Topic revision: r1 - 2014-10-22 - JimSkon
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