Computer Organization and Architecture

Exam 1 sample questions

Fall 2012

1. To transmit data bits 0110, the correct even parity seven bit Hamming Code is (bits ordered 7654321, place the 3 extra bits in location 765, e.g. P4P2P10110)

Start with P bits in locations 1, 2, 4: 011P40P2P1. Bit 1 for bits 1 3 5 7, and is thus 1, Bit 2 is for 2 3 6 7, for a 1, Bit 4 is for 4 5 6 7, for a 0. Thus we get 0110011. Putting the bits at the left (e.g. change 011P40P2P1 to P4P2P10110) , we get 0110110.

2. Compare characteristic of RAM, ROM, PROM, EPROM, EEPROM memory. What are the best uses of each?

See Chapter 3

3. A given memory chip has 22 address pins and 16 data pins. How many bits are in the memory? How many bytes? How many words? What is the smallest addressable unit?

216 = 4,194,304 words; 16*216 = 67,108,864 bits, 2*216 = 8,388,608 bytes. Smallest is a word, 16bits.

4. A given memory chip has 10 address pins and 4 data pins. Draw the chips with it's inputs. What is the size of the chip in bits/bytes? Draw a circuit using two chips to make a memory 8 bits wide. Next draw a circuit to make a memory 4-bits wide, but with twice as many 4-bit words as a single chip.

Done is class.

5. What is DRAM and SRAM? What is the advantage of each?

See Chapter 3.

6. Convert 42 and -17 to eight bit 2-s complement values.

42 = 00101010, -17 = 11101111

7. How does the bus width of a CPU affect the performance and operations of a computer. What is the difference between the address bus and data bus? What is a control bus?

See Chapter 3.

8. Suppose that a bus has 32 data lines and requires 6 cycles of 200 nsecs each to transfer data. What is the bandwidth of this bus?.

(32) / (6*200x10^-9) = 26,666,666.6667 or 26.6Mbits/sec, or 3.33Mbytes/sec

9. 7What is meant by the word size of a computer? What does this have to do with the sizes of the data and address bus?

Usually the size of the data bus.

10. What is an interrupt and what are they used for? How do they work?

See Chapter 3.

11. What is von Neumann architecture?

See Chapter 1.

12. What is propagation delay and why is it important?

See Chapter 3.

13. How can a NAND gate be used to make other gates?

See Chapter 2.

14. What I meant by microcode, microprogramming? Why is this method used?

See Chapter 4.

15. What is the significance of RISC and CISC designs? Advantages of each? How does each work?

16. Explain pipelining, superscalar processing, array processor, vector processor, caching. How does each work?

See Chapter 3.

17. A certain CPU has a two-level cache . The first-level cache has an access time of 4 nano sec, the second-level cache has an access time of 30 nano sec, and memory has an access time of 80 nano sec. If the hit ratio for the first-level cache is 80% and the hit ratio for the second-level cache is 15%, what is the mean access time for this memory system?

If simultaneous lookup then L1T * L1HR + L2T * L2HR + MT * MHT
(4 * .8) + (30 * .15) + (80 * .05) = 11.7ns
Simultaneous lookup means to start looking up in all three at the same time, using the first that gets returned.

If one at a time lookup (e.g. first try L1, then is that fails try L2, if that fails try main memory)
L1T + L2T * (1-L1HR) + MT * (1-(L1HR +L2HR)
4+ (30 * .20) + (80 * .05) = 14ns

18. Calculate the bus bandwidth required to display ful HD (1920x1080) true-color (24 bits per pixel) at 60 frames/sec. Assume that the data must pass over the bus twice, once from the hard disk to memory, and once from the memory to the video card.

1920*1080*24*60*2 bits/sec = 5,971,968,000bits/sec or 5.97Gbits/sec

19. What is word alignment, and why is it significant?
See: http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Data/aligned.html

20. Design:

• A 2x4 decoder

• A 8x1 multiplexer

• 4x4 memory circuit

See chapter 2

Topic revision: r1 - 2012-10-22 - JimSkon

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