Computer Organization and Architecture

Midterm Exam Review

Fall 2012

Calculators will be allowed.

  1. General

The final examination is comprehensive and will cover the following Sections:

  1. Chapter 1 (all)

  2. Chapter 2, sections 2.1-2.2

  3. Chapter 3, sections 3.1-3.6

  4. Chapter 4, sections 4.1-4-2

  5. The class slides.

  1. Types of Questions

The test may include the following types of questions. There will not necessarily be each type, but there will not be any type not described below.

  1. Short answer: one-two paragraph description or discussion of a concept such as the ideas of levels in computer architecture.

  1. Problem: possibilities include problems similar to those at the end of the chapters.

NOTE: There will NOT be questions asking you to write a definition for some term. Rather, it is assumed that you know the relevant terminology as presented in the text and in class. This terminology will be used in questions as needed.

  1. Key Concepts

Chapter 1

  1. Computer architecture in terms of levels, languages and virtual machines; interpretation of a level into the “language” of the level below it.

  1. Typical levels such as the application language level, etc. and the “view” presented to the user. e.g. the ISA level presents the view of machine language programming.

  1. The equivalence of hardware and software; implementation of the microarchitecture level in hardware or microprogrammed.

  1. Moore’s Law.

Chapter 2

  1. Binary, hexadecimal number systems; conversions; arithmetic; integer storage formats; bit and byte numbering.

  2. Hamming code, error correction.

  3. Memory levels (registers, cache, main, …), memory hierarchy.

  4. Memory types (Static RAM, Dynamic Ram, ROM, Prom, EPROM. EEPROM, Flash). Attribute (volatility, speed, relative size, read/write attributes)

  5. Two’s Complement Arithmetic.

  6. Instruction execution by the CPU, ALU data path and data path cycle.

  1. Advantages and disadvantages of interpreter-based architecture.

  1. RISC and CISC, differences, advantages of each, RISC design principles.

  1. Instruction-level and processor-level parallelism, pipelining, superscalar architecture, array computers, vector processors, multi-processors, and multicomputers.

  1. Memory addressing, bit/byte ordering, error-detection and correction codes, Hamming distance, Hamming codes, memory caches, mean access time for memory.

  1. Architecture below the ISA level including memory and registers: types of registers and their uses.

Chapter 3:

  1. Converting an AND-OR circuit to a NAND-NAND circuit or an OR-AND circuit to a NOR-NOR circuit.

  2. Common combinatorial circuits including multiplexers, decoders, half- and full-adders, shifters, and comparators.

  3. Combining common combinatorial circuits to make a simple ALU.

  4. Sequential circuits including D and T flip-flops/latches.

  5. Combining combinatorial and sequential circuits as needed to make registers and memory units.

  6. Combining RAM or ROM chips of certain sizes to make larger memories.

  7. Computer Buses, width, timing, timing diagrams.

  8. Asynchronous and synchronous buses.

  9. Bus arbitration and priority.

  10. Bus Pipelining

Chapter 4

  1. The concepts of microarchitecture and microcoding.

  2. Basic Mic-1 organization.

Topic revision: r1 - 2012-10-10 - JimSkon
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