Lab 6 - Memory, Buses, and manual ALU operations

Step 1 - Using a register

Logisim contains a variety of devices including a register. A simple register allows you to load data into it (if the load is set and a clock pulse ticks), and read data out of it.


SimpleReg.circ: SimpleReg .circ

To do

1.1 Build the circuit above

1.2 Explain that steps need to be taken to load data into the register.

1.3 What is the effect of the Enable input when set to 0?

1.4 The Clear input is asynchronous. What does this mean?

Step 2 - Controlling a memory

Logisim has a RAM memory device. It has three possible modes, determined in the setting for the device:

One Synchronous Load/Store port

  • A - An address bus. Set size to determine memory size in words. Use to select word for operation.
  • D - Databus. This is bi-direction, that is it can be either an input or output. Must be wired with tri-state buffers to assure that outputs are never combined. Direction determined by ld.
  • sel - Memory select. If 1, memory is active. If 0, output is always floating, memory is inactive.
  • ld - Load. If 1 then MEM[A] is output on D (read from memory). If zero, data on D is sampled, and written to MEM[A] (stored to memory). Read is asynchronous, store only occurs on clock.
  • clock - store into memory only occurs on clock pulse. (Synchronous)
  • clr - Clear all memory
One aSynchronous Load/Store port

  • Works like above, but no clock. So is ld = 1, whatever is on D is written into MEM[A] asynchronously.
Separate Load and Store ports

  • A - An address bus. As above
  • Din - Input Databus.
  • Dout - output Databus.
  • sel - Memory select.
  • ld - Load. If 1 then MEM[A] is output on Dout (read from memory).
  • str Store - If 1, the data on Din is sampled, and written to MEM[A] (stored to memory), store only occurs on clock.
  • clock - store into memory only occurs on clock pulse. (Synchronous)
Below is small circuit with a memory device set up to read from data in, and output to a probe, based on a the selections of a set of inputs. The address size is 8-bits, and the word size is also 8 bits. (the default for Logisim)

The probe can be set to different radixes. Here the radix is set to decimal.

To do:

Step 2.1

  1. Build the circuit above, and get it working.
  2. How many memory words are in this memory? How do you know?
  3. Explain what steps need to be taken to write something into memory.
  4. Explain what steps need to be taked to read something from memory.
  5. Write a 0x12 into location 1, 0x4 into location 2, and 0x7 into location 4.
  6. Read memory location 2.
  7. Paste a view of the circuit in the current state into the lab report.
  8. What is the purpose and function of the two tri-state buffers?
Step 2.2

  1. Build a version of the circuit using an asynchronous load/store.
  2. How is the use of this system different? What are some of the reasons a clock might be a good idea?
  3. Load this memory with the same values as above. Paste a view of the circuit in the current state into the lab report.

Step 3.3
  1. Build a version of the circuit using the version with separate Load and Store ports
  2. How is the use of this system different from the previous two?
  3. What happens if you try to read and write at the same time?
  4. Load this memory with the same values as above. Paste a view of the circuit in the current state into the lab report.

Step 3 - Creating a bus

Buses are useful for carrying data between devices. The main rule of a bus is thatonly one device can write at a time, while any number of devices can read from it at a time.

Below I have created a simple data bus with 4 inputs - a manual input, a memory, and two registers (labeled A and B). The registers have an input (D), an output (Q), an enable (en), and a clock input.

Note that the data destination can be set for more than one device. But the data source goes through a decoder which determines which devices output is placed on the bus.


To do:

Step 3.1
  1. Build the circuit above, and get it working.
  2. Load 0x21 into memory location 0x4, 0x3 into Register A and 0x53 into Register B.
  3. Paste a picture of the machine into the lab report.
  4. Why are the tri-state gates used?
  5. What is the purpose of the OR gate below the memory?
  6. Whay use a decoder for the input select? Why not just have four input bits, as is done for the destination select?

Step 4 - Adding an ALU

The goal here is to add the ALU from the previous lab, allowing the system to perform computations on demand.

To make sure we all have functional ALU's, I am giving you the solution to the ALU from the previous Lab below:


We wish to create an ALU with the following functions: The three function bits should cause the 12-bit ALU to do the following operations:
Function Bits Operation
0 (0,0,0) B
1 (0,0,1) A
2 (0,1,0) B'
3 (0,1,1) A^B
4 (1,0,0) AvB
5 (1,0,1) A + B + Cin
6 (1,1,0) -A
7 (1,1,1) B - A

Note that A+ Cin and B + Cin give us multiple functions. If Cin is 0, the A or B inputs is simply passed through. Otherwise the value is incremented.

Below is the start of such a integration. Notice that the ALU from the previous project has been wired into the bus. Also note that the size of the databus, and all data components has been increased to 12 bits for compatibility.

The A register is connected to the A input of the ALU. The databus is connected to the B input of the ALU. Thus we can now put something in A register, and place a value from memory, A reg, or B reg on the B input of the ALU. We can select a function for the ALU. The output of the ALU is connected to a probe.


The problem with this design is the we cannot send data to the ALU on it's A input, and then read it back on the same bus at the same time. So there is really no way to load the result if the ALU operation back into the registers or memory.

The solution? We really need TWO separate buses, an A bus to send the data to the ALU, and a B bus to bring it back to the devices. We can make the outputs of all the devices connect to the A bus, and then connect the inputs of all the devices to the B bus.

However - there is now no DIRECT path from one device to another. The only path to transfer data from one device to another is to go through the ALU. It's a good thing we have the two functions in the that simply pass either the A or B input directly to the output. Thus we can, by selecting the appropriate ALU function, transfer any input device's value to any output device.

To do:

Step 4.1
  1. Build the circuit above, and get it working Make sure you can get the ALU to receive it's input from any device.
  2. Modify the circuit so that there are two buses. One (the A bus) is connected to the outputs of the devices (memory, input, registers), and the other (the B bus) is connected to the inputs of the devices. The destination and source logic should remain untouched.

    Then set up the ALU to have the new A bus connected to the A input on the ALU. Thus the destination logic will choose which device sends it's output to the A input of the ALU. (The B input of the ALU will ALWAYS come from the A register, as shown).

    Next, set up the output of the ALU to go to the new B bus. The destination logic will now determine which device(s) receive the data on the B bus.

    Now, as mentioned above, all data transfers will pass through the ALU.

  3. Make sure everything works.
  4. Take a picture of the device, and paste it in your lab report.

Step 4.2
  1. Explain what needs to be done to transfer data from the input to a address in Memory
  2. Explain how Data can be transferred from Memory to a register.
  3. Explain out the output of the ALU can be passed to Memory or the registers.
  4. Can the Memory, and both registers all get updates at once? How.

Step 4.3
  1. Explain (and actually do) the following steps:
    1. Take 0x3 and put it in memory location 0x0
    2. Take 0x7 and put it in memory location 0x1
    3. Transfer memory location 0x0 to register B
    4. Transfer Memory location 0x1 to register A
    5. Add register B to A, and put the result in Memory location 0x3
  2. Show the system after completing this task.

Step 5 - Adding an MAR and ACC

What if we wish to get the memory address from a register rather then from an input? Then we could have the concept of a register point to a place in memory. In this section we will add a MAR - a Memory Address Register.

Step 5.1
  1. What if you needed more registers? Before we add a MAR, let us add two more registers.
    1. Modify your system to have 4 registers. Let's call them MAR, B, C, ACC
    2. Make ACC always be the B input on the ALU
    3. Make the A input of the ALU come from the any one of the register, the memory, or the input.
    4. Test out your system
    5. Explain how the MAR could be incremented to step through an "array" in memory to access the elements one at a time. How can you increment a register with this system?
    6. Take a picture of your modified system and include it in the lab report

Step 5.2
  1. Remove the address input pad. Instead make the address for memory to always come from the MAR. But there is a problem - the register is 12 bit but their are only 8 address lines. The solution - use a splitter to branch off the low 8 bits, and ignore the top 4 bits of the MAR.
  2. Test your system out to make sure it works.
  3. Is it possible to set the MAR from a value entered into the data input? How?
  4. Example how you could now sum the contents of the first three locations in memory, M[0], M[1], M[2] and put the result in M[3].
  5. Take a screenshot of your computer after doing the step above, and include it in your lab report.
What do you think of your simple computer? Or is it a computer? What does this system lack to be considered a computer?


Topic attachments
I Attachment Action Size Date Who Comment
Circcirc ALU.circ manage 12.5 K 2014-10-06 - 02:37 JimSkon Complete ALU
Circcirc ALU9.circ manage 11.6 K 2014-11-04 - 20:58 JimSkon  
Pngpng ALU9.png manage 29.0 K 2014-11-04 - 21:01 JimSkon  
Pngpng CompleteALU.png manage 14.3 K 2014-10-06 - 02:35 JimSkon  
Pngpng MemoryBusALU.png manage 15.9 K 2014-09-23 - 04:25 JimSkon  
Pngpng SimpleBus.png manage 11.0 K 2014-09-23 - 03:29 JimSkon  
Circcirc SimpleReg.circ manage 3.1 K 2014-10-14 - 20:30 JimSkon  
Pngpng SimpleReg.png manage 10.8 K 2014-10-14 - 20:29 JimSkon  
Pngpng memoryexample.png manage 5.6 K 2014-09-23 - 02:34 JimSkon  
Htmlhtml microcode.html manage 1.7 K 2014-09-29 - 13:22 JimSkon Microcode generator
Topic revision: r14 - 2014-11-05 - JimSkon
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